Numerical Study of Partial-SOI LDMOSFET Power Devices

Smart power ICs, which monolithically integrate low-loss power devices and control circuitry, have attracted much attention in a wide variety of applications [1], [2]. Commonly used smart power devices are the LDMOS and LIGBT implemented in bulk silicon or SOI (Silicon on Insulator). One of the key issues in the realization of such ‘smart power’ technology is the isolation of power devices and low-voltage circuitry. SOI technology consistutes an attractive alternative to the traditional junction isolation. When high-voltage devices over 100 V are integrated on an SOI wafer, the isolation area between devices shrinks and lower leakage currents result in greatly improved high temperature performance. In general the breakdown voltage of an SOI structure is a function of the thickness of the silicon and the buried oxide layer [1]. The buried oxide helps to sustain a high electric field which results in a higher breakdown voltage. However, the operation of SOI power devices is limited by self-heating effects during switching and some fault conditions such as short circuit. Since the buried oxide underneath the device is a good thermal insulator, the temperature rise inside SOI power devices can be much higher than that of bulk silicon devices. Self-heating of SOI power devices can result in serious reliability problems during operation in a high temperature environment. To solve this problem, partial-SOI (P-SOI) technology was suggested [3], [4], where a silicon window helps to reduce self-heating. In addition, potential lines spread into the substrate. Therefore it is possible to obtain higher breakdown voltages than those of conventional SOI devices, because the depletion layer in the substrate supports some voltage. This paper discusses the dependence of the breakdown voltage and temperature distribution on the location of the silicon window. We numerically confirm that the breakdown voltage of P-SOI LDMOSFET with a silicon window under the source is higher than that of P-SOI LDMOSFET with a silicon window under the drain.